{
  "slug": "adr",
  "term": "Asynchronous DRAM Refresh",
  "aliases": [
    "ADR"
  ],
  "definition": "Asynchronous DRAM Refresh is a platform power-fail mechanism that drains covered memory-controller write-pending buffers to persistent memory without protecting dirty CPU caches.",
  "note": "In Intel's documented persistent-memory platform, data that reaches the covered controller queue can survive power loss, while cache-resident updates require software persistence operations. [intel-adr] The name does not mean ordinary DRAM automatically becomes nonvolatile; protection depends on the platform and backing medium. eADR extends the protected boundary to CPU caches. [intel-eadr]",
  "status": "shipping",
  "advantages": [],
  "limitations": [],
  "related": [
    "persistence-domain",
    "eadr",
    "persistent-memory",
    "persistence-ordering"
  ],
  "supersedes": [],
  "supersededBy": [],
  "firstSeen": null,
  "lastSeen": null,
  "updated": "2026-10-13",
  "citations": [
    {
      "id": "intel-adr",
      "title": "Intel. Second Generation Xeon Processor Scalable Family Technical Overview: The Persistence Domain.",
      "url": "https://www.intel.com/content/www/us/en/developer/articles/news/second-generation-intel-xeon-processor-scalable-family-technical-overview.html",
      "accessed": "2026-10-13"
    },
    {
      "id": "intel-eadr",
      "title": "Intel. Third Generation Xeon Processor Scalable Family on Two Socket Platforms: eADR.",
      "url": "https://www.intel.com/content/www/us/en/developer/articles/technical/third-generation-xeon-scalable-family-overview.html",
      "accessed": "2026-10-13"
    },
    {
      "id": "hesela-pmem",
      "title": "Hesela. Persistent memory: DAX is not a durable commit.",
      "url": "https://hesela.com/analyses/pmem-persistence-domains-dax/",
      "accessed": "2026-10-13"
    }
  ]
}