{
  "slug": "controller-memory-buffer",
  "term": "Controller Memory Buffer (CMB)",
  "aliases": [
    "CMB"
  ],
  "definition": "Controller Memory Buffer is an optional NVMe mechanism that exposes controller-resident memory for host use through PCIe.",
  "note": "The controller advertises supported uses, which may include queues, descriptors or transfer data. HMB instead assigns host memory to the controller. CMB is not a synonym for an SSD's private DRAM cache. [nvme]",
  "status": "shipping",
  "advantages": [
    {
      "text": "Supported queue and descriptor placement can avoid fetching these structures from host memory.",
      "citationIds": [
        "nvme"
      ]
    }
  ],
  "limitations": [
    {
      "text": "Available uses depend on controller capability flags; CMB does not itself establish persistent-memory or power-loss-protection guarantees.",
      "citationIds": [
        "nvme"
      ]
    }
  ],
  "related": [
    "hmb",
    "nvme",
    "pcie-storage",
    "dram-cache-ssd"
  ],
  "supersedes": [],
  "supersededBy": [],
  "firstSeen": null,
  "lastSeen": null,
  "citations": [
    {
      "id": "nvme",
      "title": "NVM Express 1.4a (9 March 2020), sections 4.7 and 4.8: CMB and PMR. Copyright 2007-2020 NVM Express, Inc.",
      "url": "https://www.nvmexpress.org/wp-content/uploads/NVM-Express-1_4a-2020.03.09-Ratified.pdf",
      "accessed": "2026-10-18"
    },
    {
      "id": "hesela-hmb",
      "title": "Hesela: Host Memory Buffer (HMB).",
      "url": "https://hesela.com/tech/hmb/",
      "accessed": "2026-10-18"
    }
  ],
  "updated": "2026-10-18"
}