{
  "slug": "dftl",
  "term": "DFTL",
  "aliases": [
    "Demand-based Flash Translation Layer"
  ],
  "definition": "DFTL is a research flash translation layer that caches selected page-level address mappings in RAM while keeping mapping pages on flash.",
  "note": "The Cached Mapping Table holds selected data-page mappings; the Global Translation Directory locates their translation pages. Mapping granularity and RAM residency are separate choices. [dftl2009]\n\nAn unchanged victim can be discarded without metadata writeback. A modified victim requires a translation-page update and directory adjustment. [dftl2009]\n\nDemand caching favors temporal reuse; the original implementation uses segmented LRU. DFTL names a specific design, not every partially cached FTL. [dftl2009]",
  "status": "research",
  "advantages": [],
  "limitations": [
    {
      "text": "The original evaluation uses FlashSim and workload traces; its results do not establish the performance of current commercial SSDs.",
      "citationIds": [
        "dftl2009"
      ]
    }
  ],
  "related": [
    "global-translation-directory",
    "mapping-cache",
    "page-level-mapping",
    "translation-page",
    "ftl",
    "tpftl",
    "s-ftl"
  ],
  "supersedes": [],
  "supersededBy": [],
  "firstSeen": null,
  "lastSeen": null,
  "updated": "2026-11-09",
  "citations": [
    {
      "id": "dftl2009",
      "title": "Gupta, Kim and Urgaonkar. DFTL: A Flash Translation Layer Employing Demand-based Selective Caching of Page-level Address Mappings. ASPLOS 2009.",
      "url": "https://doi.org/10.1145/1508244.1508271",
      "accessed": "2026-11-09"
    },
    {
      "id": "mapping-guide",
      "title": "Hesela: SSD mapping caches and host memory",
      "url": "https://hesela.com/analyses/ssd-mapping-cache-hmb/",
      "accessed": "2026-11-09"
    }
  ],
  "provenance": [
    "Source synthesis from the original paper, sections 3-5; no experiment reproduced here."
  ]
}