{
  "slug": "execute-in-place",
  "term": "Execute-in-place",
  "aliases": [
    "XIP",
    "eXecute-In-Place",
    "execute in place"
  ],
  "definition": "Execution of program instructions from their non-volatile storage location without first copying the executable code into a separate RAM image.",
  "note": "The system must provide an instruction-fetch path to the stored code. With serial flash, a controller can translate memory-mapped reads into flash transactions after the interface and read mode are configured. A chip's NOR label alone does not establish a working execute-in-place system. [c1]\n\nExecute-in-place does not eliminate RAM: caches, writable data, stacks and other runtime state can still use it. For a memory-mapped read-only filesystem, directly executed segments may require uncompressed, aligned storage while writable segments are copied to RAM. This differs from mapping a file backed by an SSD and fetching its pages into memory. [c2]\n\nSome flash documentation also calls a command-saving continuous-read mode XIP. That device feature can reduce read-command overhead, but it is not the complete system mechanism for executing stored instructions. [c1]",
  "status": "shipping",
  "advantages": [
    {
      "text": "Code can remain in non-volatile storage when RAM capacity is constrained.",
      "citationIds": [
        "c2"
      ]
    }
  ],
  "limitations": [
    {
      "text": "An update must account for program/erase activity that can block instruction reads from the same flash device.",
      "citationIds": [
        "c3"
      ]
    }
  ],
  "related": [
    "nor-flash",
    "nand-flash",
    "byte-addressable-storage",
    "memory-mapped-file",
    "page-cache"
  ],
  "supersedes": [],
  "supersededBy": [],
  "firstSeen": null,
  "lastSeen": null,
  "updated": "2026-10-18",
  "citations": [
    {
      "id": "c1",
      "title": "STMicroelectronics. AN4760, Quad-SPI interface for STM32 MCUs and MPUs, revision 5, sections 3.3.3, 3.4.1 and 6.2: execution and continuous read.",
      "url": "https://www.st.com/resource/en/application_note/an4760-introduction-to-quadspi-interface-for-stm32-mcus-and-mpus-stmicroelectronics.pdf",
      "accessed": "2026-10-18"
    },
    {
      "id": "c2",
      "title": "Linux kernel documentation. Cramfs: Memory Mapped cramfs image. Direct execution of aligned, uncompressed read-only segments and RAM for writable data.",
      "url": "https://docs.kernel.org/filesystems/cramfs.html#memory-mapped-cramfs-image",
      "accessed": "2026-10-18"
    },
    {
      "id": "c3",
      "title": "Infineon. Implementation of Program/Erase Suspend and Resume Operations in Serial NOR Flash. Busy-array access and suspend restrictions.",
      "url": "https://community.infineon.com/t5/Knowledge-Base-Articles/Implementation-of-Program-Erase-Suspend-and-Resume-Operations-in-Serial-NOR/ta-p/256736",
      "accessed": "2026-10-18"
    }
  ]
}