{
  "slug": "interrupt-coalescing",
  "term": "Interrupt coalescing",
  "aliases": [
    "Interrupt aggregation",
    "Interrupt moderation"
  ],
  "definition": "Interrupt coalescing groups completion notifications to reduce interrupt frequency without combining the underlying I/O commands.",
  "note": "In NVMe over PCIe, posting a completion entry and signaling an interrupt are distinct events. Coalescing reduces notification frequency and can increase notification delay; host software still processes individual completion entries. [pcie] In the cited delayed-hit model, cache request coalescing instead lets pending requests for the same object share one in-flight fetch [latency-pipeline].\n\nBase 2.0d feature 08h applies to I/O queues, not the Admin completion queue. Either TIME = 0 or THR = 0 disables coalescing. Otherwise, TIME uses 100-microsecond increments and THR is zero-based. Feature 09h can disable coalescing separately for an interrupt vector [base].\n\nThe time and threshold settings are recommendations, not strict latency bounds. CQ-head updates may restart aggregation while completions are being processed, delaying further interrupts. Do not infer completed-command counts or a hard application deadline from interrupt counts or coalescing settings [base].",
  "related": [
    "nvme",
    "nvme-completion-queue",
    "io-completion-polling",
    "request-coalescing"
  ],
  "citations": [
    {
      "id": "pcie",
      "title": "NVM Express PCIe Transport 1.0d, sections 3.2, 3.4.1 and 3.5; copyright 2008-2023 NVM Express, Inc., all rights reserved",
      "url": "https://nvmexpress.org/wp-content/uploads/NVM-Express-PCIe-Transport-Specification-1.0d-2023.12.27-Ratified.pdf",
      "accessed": "2026-10-20"
    },
    {
      "id": "base",
      "title": "NVM Express Base 2.0d, sections 5.27.1.6-5.27.1.7; copyright 2008-2024 NVM Express, Inc., all rights reserved",
      "url": "https://nvmexpress.org/wp-content/uploads/NVM-Express-Base-Specification-2.0d-2024.01.11-Ratified.pdf",
      "accessed": "2026-10-20"
    },
    {
      "id": "latency-pipeline",
      "title": "Keren et al. Latency-Aware Caching with Delayed Hits: From Bursty Traffic to Pipeline Architectures. NSDI 2026, sections 1.1 and 4.",
      "url": "https://www.usenix.org/system/files/nsdi26-keren.pdf",
      "accessed": "2026-10-19"
    }
  ],
  "status": "shipping",
  "advantages": [],
  "limitations": [],
  "supersedes": [],
  "supersededBy": [],
  "firstSeen": null,
  "lastSeen": null,
  "updated": "2026-10-20",
  "provenance": [
    "Mechanism explained using versioned NVMe PCIe and Base specifications; other devices have their own controls.",
    "Source review, not a measurement of interrupt frequency, CPU cost or device latency."
  ]
}