{
  "slug": "nvme-completion-queue",
  "term": "NVMe completion queue",
  "aliases": [
    "NVMe CQ",
    "NVMe PCIe completion queue"
  ],
  "definition": "On the NVMe PCIe path, a completion queue is a memory ring where a controller posts command results for host software.",
  "note": "A completion identifies its command by submission-queue ID and command ID. Completion order need not follow submission order. SQHD is a separate slot-consumption report, not a list of completed commands [base].\n\nThe phase bit distinguishes the expected traversal of the ring, not successful status. Linux v6.12 checks that bit, applies a DMA read barrier before handling the rest of the entry, and changes its expected phase when the completion head wraps [linux].\n\nA full completion queue prevents further status posting there. The controller may pause associated submission queues until slots are returned, but this condition must not stop unrelated submission queues [base].\n\nPosting a completion entry is separate from notifying the host. An interrupt can prompt processing of several entries; polling can inspect the queue without waiting for that interrupt. Coalescing changes notification frequency, not completion identity [pcie].",
  "related": [
    "nvme",
    "nvme-submission-queue",
    "nvme-doorbell",
    "queue-depth",
    "interrupt-coalescing",
    "io-completion-polling",
    "nvme-phase-tag",
    "nvme-command-identifier"
  ],
  "citations": [
    {
      "id": "base",
      "title": "NVM Express Base 2.0a, sections 2.1-2.2, 3.1.1, 3.3.1.2 and 3.3.3.2; copyright 2007-2021 NVM Express, Inc., all rights reserved",
      "url": "https://nvmexpress.org/wp-content/uploads/NVMe-NVM-Express-2.0a-2021.07.26-Ratified.pdf",
      "accessed": "2026-10-20"
    },
    {
      "id": "linux",
      "title": "Linux v6.12: NVMe PCIe queue submission, completion handling and doorbell-buffer checks",
      "url": "https://github.com/torvalds/linux/blob/v6.12/drivers/nvme/host/pci.c",
      "accessed": "2026-10-20"
    },
    {
      "id": "pcie",
      "title": "NVM Express PCIe Transport 1.0d, sections 3.2, 3.4.1 and 3.5; copyright 2008-2023 NVM Express, Inc., all rights reserved",
      "url": "https://nvmexpress.org/wp-content/uploads/NVM-Express-PCIe-Transport-Specification-1.0d-2023.12.27-Ratified.pdf",
      "accessed": "2026-10-20"
    }
  ],
  "status": "shipping",
  "advantages": [],
  "limitations": [],
  "supersedes": [],
  "supersededBy": [],
  "firstSeen": null,
  "lastSeen": null,
  "updated": "2026-10-23",
  "provenance": [
    "The memory-ring description is PCIe-scoped; NVMe over Fabrics uses transport-specific messaging.",
    "Historical specification and pinned implementation references describe mechanisms, not current feature coverage or measured performance."
  ]
}