{
  "slug": "nvme-doorbell",
  "term": "NVMe doorbell",
  "aliases": [
    "NVMe PCIe doorbell",
    "SQ tail doorbell",
    "CQ head doorbell"
  ],
  "definition": "An NVMe PCIe doorbell communicates a submission-queue tail or completion-queue head position from host software to the controller.",
  "note": "An SQ-tail update announces submitted commands. A CQ-head update returns consumed completion slots for reuse. Either update can cover a batch; it is not a transfer of the command or read/write payload itself [spdk]. Reading a CQ entry alone does not release its slot; the controller needs the updated head [base].\n\nLinux v6.12 writes the tail or head value through distinct PCIe register locations. With doorbell-buffer support configured, its event-index check can avoid a register write. Counting MMIO doorbell writes therefore does not directly count I/O commands [linux].",
  "related": [
    "nvme",
    "nvme-submission-queue",
    "nvme-completion-queue",
    "pcie-storage"
  ],
  "citations": [
    {
      "id": "spdk",
      "title": "SPDK: Submitting I/O to an NVMe Device",
      "url": "https://spdk.io/doc/nvme_spec.html",
      "accessed": "2026-10-20"
    },
    {
      "id": "linux",
      "title": "Linux v6.12: NVMe PCIe queue submission, completion handling and doorbell-buffer checks",
      "url": "https://github.com/torvalds/linux/blob/v6.12/drivers/nvme/host/pci.c",
      "accessed": "2026-10-20"
    },
    {
      "id": "base",
      "title": "NVM Express Base 2.0a, section 3.3.1.2; copyright 2007-2021 NVM Express, Inc., all rights reserved",
      "url": "https://nvmexpress.org/wp-content/uploads/NVMe-NVM-Express-2.0a-2021.07.26-Ratified.pdf",
      "accessed": "2026-10-20"
    }
  ],
  "status": "shipping",
  "advantages": [],
  "limitations": [],
  "supersedes": [],
  "supersededBy": [],
  "firstSeen": null,
  "lastSeen": null,
  "updated": "2026-10-20",
  "provenance": [
    "The memory-ring description is PCIe-scoped; NVMe over Fabrics uses transport-specific messaging.",
    "Historical specification and pinned implementation references describe mechanisms, not current feature coverage or measured performance."
  ]
}