{
  "slug": "nvme-prp",
  "term": "NVMe Physical Region Page",
  "aliases": [
    "NVMe PRP",
    "Physical Region Page"
  ],
  "definition": "An NVMe Physical Region Page entry identifies a memory page or page portion used to transfer a command's data buffer.",
  "note": "For ordinary PRP-based Read and Write commands, PRP1 can start within the first memory page. When PRP1 alone is insufficient, PRP2 identifies a second data page or a list of additional page addresses [nvme-1-0e]. The page is transfer memory, not NAND geometry.\n\nWith a 4 KiB controller memory page, an 8 KiB transfer starting at offset zero spans two pages; at offset 512 it spans three and needs a PRP list. This is address-span arithmetic, not a speed measurement [linux-pci].\n\nOn PCIe, buffer pointers contain device-visible DMA addresses, which an IOMMU can translate; an application pointer is not directly interchangeable with them [linux-dma].\n\nList storage is separate: the initial list pointer may be 8-byte aligned within a page; later list pages are page-aligned. A page-aligned 4 KiB list has 512 slots, but a non-final list spends one on a link, leaving 511 data addresses. A nonzero starting offset reduces its slots [nvme-base-2-0a].",
  "status": "shipping",
  "advantages": [],
  "limitations": [],
  "supersedes": [],
  "supersededBy": [],
  "firstSeen": null,
  "lastSeen": null,
  "updated": "2026-10-17",
  "related": [
    "nvme",
    "nvme-sgl"
  ],
  "provenance": [
    "The Read/Write rules are checked in NVMe 1.0e; Linux v6.12 independently shows the first-page remainder and list construction [nvme-1-0e] [linux-pci].",
    "The 4 KiB example is illustrative, not a universal page-size requirement or a hardware test."
  ],
  "citations": [
    {
      "id": "nvme-1-0e",
      "title": "NVM Express 1.0e: revision history and PRP-based Read/Write; copyright 2007-2014 NVM Express, Inc., all rights reserved",
      "url": "https://nvmexpress.org/wp-content/uploads/NVM-Express-1_0e.pdf",
      "accessed": "2026-10-17"
    },
    {
      "id": "nvme-base-2-0a",
      "title": "NVM Express Base 2.0a, sections 2 and 4.1; copyright 2007-2021 NVM Express, Inc., all rights reserved",
      "url": "https://nvmexpress.org/wp-content/uploads/NVMe-NVM-Express-2.0a-2021.07.26-Ratified.pdf",
      "accessed": "2026-10-17"
    },
    {
      "id": "linux-pci",
      "title": "Linux v6.12: NVMe PCIe data mapping and PRP/SGL construction",
      "url": "https://github.com/torvalds/linux/blob/v6.12/drivers/nvme/host/pci.c",
      "accessed": "2026-10-17"
    },
    {
      "id": "linux-dma",
      "title": "Linux 6.12: Dynamic DMA mapping guide, CPU and DMA addresses",
      "url": "https://docs.kernel.org/6.12/core-api/dma-api-howto.html",
      "accessed": "2026-10-17"
    },
    {
      "id": "hesela-nvme",
      "title": "Hesela: NVM Express technology card",
      "url": "https://hesela.com/tech/nvme/",
      "accessed": "2026-10-17"
    }
  ]
}