{
  "slug": "nvme-submission-queue",
  "term": "NVMe submission queue",
  "aliases": [
    "NVMe SQ",
    "NVMe PCIe submission queue"
  ],
  "definition": "On the NVMe PCIe path, a submission queue is a memory ring where host software places commands for a controller to consume.",
  "note": "The command ring is separate from read/write payload buffers. Host software fills free command slots and publishes a new tail position through a doorbell, which can announce several commands together [spdk].\n\nEach I/O submission queue has an associated completion queue; several I/O submission queues may share one. The Admin queues remain one-to-one. An advancing SQHD reports consumed command slots, not completed commands [base].\n\nSQHD is captured when the completion entry is created; the controller may have consumed more slots before the host reads that entry [base].",
  "related": [
    "nvme",
    "nvme-completion-queue",
    "nvme-doorbell",
    "nvme-prp",
    "nvme-sgl",
    "queue-depth",
    "nvme-command-identifier"
  ],
  "citations": [
    {
      "id": "spdk",
      "title": "SPDK: Submitting I/O to an NVMe Device",
      "url": "https://spdk.io/doc/nvme_spec.html",
      "accessed": "2026-10-20"
    },
    {
      "id": "base",
      "title": "NVM Express Base 2.0a, sections 2.1-2.2, 3.1.1, 3.3.1.2 and 3.3.3.2; copyright 2007-2021 NVM Express, Inc., all rights reserved",
      "url": "https://nvmexpress.org/wp-content/uploads/NVMe-NVM-Express-2.0a-2021.07.26-Ratified.pdf",
      "accessed": "2026-10-20"
    }
  ],
  "status": "shipping",
  "advantages": [],
  "limitations": [],
  "supersedes": [],
  "supersededBy": [],
  "firstSeen": null,
  "lastSeen": null,
  "updated": "2026-10-23",
  "provenance": [
    "The memory-ring description is PCIe-scoped; NVMe over Fabrics uses transport-specific messaging.",
    "Historical specification and pinned implementation references describe mechanisms, not current feature coverage or measured performance."
  ]
}