{
  "slug": "page-level-mapping",
  "term": "Page-level mapping (FTL)",
  "aliases": [
    "Page-mapped FTL"
  ],
  "definition": "Page-level mapping assigns physical flash locations independently to logical pages.",
  "note": "Mapping granularity does not require full RAM residency. DFTL caches selected entries. Do not equate the logical mapping unit with one host LBA or assume one fixed NAND page size. [dftl]",
  "status": "shipping",
  "advantages": [],
  "limitations": [],
  "related": [
    "ftl",
    "block-level-mapping",
    "mapping-cache",
    "translation-page"
  ],
  "supersedes": [],
  "supersededBy": [],
  "firstSeen": null,
  "lastSeen": null,
  "updated": "2026-10-18",
  "citations": [
    {
      "id": "dftl",
      "title": "Gupta, Kim and Urgaonkar. DFTL: Demand-based Selective Caching of Page-level Address Mappings. ASPLOS 2009, sections 2-3.",
      "url": "https://doi.org/10.1145/1508244.1508271",
      "accessed": "2026-10-18"
    },
    {
      "id": "ftl-guide",
      "title": "Hesela: Flash Translation Layer technology guide",
      "url": "https://hesela.com/tech/ftl/",
      "accessed": "2026-10-18"
    }
  ]
}