{
  "slug": "pcie-flit",
  "term": "PCIe FLIT",
  "aliases": [
    "PCIe flow control unit",
    "PCIe Flit Mode"
  ],
  "definition": "A PCIe FLIT is a fixed-size flow-control unit used in PCI Express Flit Mode to carry transaction packets together with link-control and error-protection information.",
  "note": "PCI-SIG documents the same 256-byte layout for PCIe 6.0 and 7.0: 236 bytes for Transaction Layer Packets (TLPs), 6 for Data Link Layer Payload (DLP), 8 for CRC and 6 for forward error correction (FEC) [c1]. The TLP region includes packet headers, so 236/256 is not application-data efficiency.\n\nPacket boundaries need not coincide with FLIT boundaries. A FLIT can carry multiple TLPs or only part of one, and a TLP can span FLITs [c2]. This fixed framing supports link error protection; it does not define an NVMe command, logical block, persistence guarantee or SSD transfer rate.\n\nThe link can retain FLIT mode after reducing its speed [c2]. Therefore a rate alone does not justify applying the earlier 128b/130b non-FLIT formula. See the storage-interface-payload-ceilings dataset for explicit accounting fields.",
  "status": "unknown",
  "advantages": [
    {
      "text": "Fixed-size framing supports the link's CRC and FEC mechanisms.",
      "citationIds": [
        "c1"
      ]
    },
    {
      "text": "TLPs can be packed across FLIT boundaries rather than requiring one FLIT per transaction.",
      "citationIds": [
        "c2"
      ]
    }
  ],
  "limitations": [
    {
      "text": "The TLP byte region still includes headers and can be incompletely occupied; its capacity is not measured application throughput.",
      "citationIds": [
        "c2"
      ]
    },
    {
      "text": "FLIT-mode accounting differs from earlier non-FLIT line encoding even when a link operates at a lower speed.",
      "citationIds": [
        "c2"
      ]
    }
  ],
  "related": [
    "pcie-storage",
    "pcie-gen5",
    "nvme"
  ],
  "supersedes": [],
  "supersededBy": [],
  "firstSeen": null,
  "lastSeen": null,
  "citations": [
    {
      "id": "c1",
      "title": "PCI-SIG: PCIe 7.0 specification webinar Q&A (3 September 2025), question 1",
      "url": "https://pcisig.com/blog/pcie-70-specification-next-generation-performance-meet-needs-advanced-ai-applications-webinar",
      "accessed": "2026-10-20"
    },
    {
      "id": "c2",
      "title": "PCI-SIG: PCIe 6.0 webinar Q&A on FLIT mode (19 August 2021), introduction and questions 3, 6-9",
      "url": "https://pcisig.com/blog/pcie%C2%AE-60-specification-webinar-qa-deeper-dive-flit-mode-pam4-and-forward-error-correction-fec",
      "accessed": "2026-10-20"
    }
  ],
  "updated": "2026-10-20",
  "provenance": [
    "This entry explains the published protocol; status does not assert device availability."
  ]
}