{
  "slug": "temporary-read-errors",
  "term": "Temporary read errors (NAND)",
  "aliases": [
    "TRE",
    "NAND temporary read errors"
  ],
  "definition": "Temporary read errors are a reversible excess of raw bit errors observed in initial reads of some 3D NAND blocks after an idle interval.",
  "note": "Zambelli et al. characterized commercial TLC 3D NAND using multiple blocks and dies of one product, with chip error correction disabled. The effect depended on the read sequence, temperature and delay between reads; it is distinct from accumulated read disturbance and early retention charge loss. [tre]\n\nTheir system-level latency and soft-decoding results were simulated, not measured on a finished SSD. A better second read does not establish relocation, durable repair or safe data acceptance without ECC. Host caches and controller policy can hide the physical read sequence. [tre] [hesela]",
  "status": "shipping",
  "advantages": [],
  "limitations": [
    {
      "text": "The study does not establish a universal retry interval, a fleet incidence rate or a unique microscopic cause.",
      "citationIds": [
        "tre"
      ]
    }
  ],
  "related": [
    "3d-nand",
    "read-disturb",
    "read-retry",
    "read-reclaim",
    "early-retention-loss",
    "soft-decision-decoding"
  ],
  "supersedes": [],
  "supersededBy": [],
  "firstSeen": null,
  "lastSeen": null,
  "updated": "2026-10-18",
  "citations": [
    {
      "id": "tre",
      "title": "Zambelli et al. Temporary read errors in TLC 3D NAND after idle. JEDS 8 (2020), 99-104. DOI: 10.1109/JEDS.2020.2965648.",
      "url": "https://doi.org/10.1109/JEDS.2020.2965648",
      "accessed": "2026-10-18"
    },
    {
      "id": "hesela",
      "title": "Hesela: first-read-after-idle measurement within SSD read-reclaim evidence",
      "url": "https://hesela.com/analyses/ssd-read-reclaim-hidden-writes/#first-read-after-idle",
      "accessed": "2026-10-18"
    }
  ]
}