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Dataset · FAST 2013 · FAST 2016

An example BCH code corrects raw bit error rates up to 1e-3, yet Google's field SSDs had median rates of 6e-10 to 3e-8, and raw rate did not predict uncorrectable errors

An example BCH code corrects raw bit error rates up to 1.0e-3 and soft LDPC up to 5.0e-3 (Cai et al., 2017; Zhao et al., FAST 2013 find about 3 times). Google's field median raw bit error rate was 5.8e-10 to over 3e-8, and 2 to 6 per 1,000 drive days had an uncorrectable error (Schroeder et al., FAST 2016).

Download CSV13 rows · 7 columns · CSV

File /data/datasets/nand-ecc-bch-vs-ldpc.csv · JSON metadata · All datasets · Human-readable note on hesela.com

Method

The figures are copied from the PDFs of Zhao, Zhao, Sun, Zhang, Zhang, and Zheng, FAST 2013, from the arXiv version of Cai, Ghose, Haratsch, Luo, and Mutlu, Proceedings of the IEEE 2017, and from Schroeder, Lagisetty, and Merchant, FAST 2016, not refit. Zhao et al. measure 25nm MLC NAND chips and drive a trace-based simulator of an SSD with a rate-8/9 LDPC code. Cai et al. is a survey whose BCH and LDPC strength curves are an example for similar codeword lengths and code rates. Schroeder et al. report raw bit error rates and uncorrectable errors from drives in Google data centers. The comparison of code limits with field error rates is this page's own and is made only to show orders of magnitude. Sources opened for this table: LDPC-in-SSD: Making Advanced Error Correction Codes Work Effectively in Solid State Drives, Zhao, Zhao, Sun, Zhang, Zhang, and Zheng, USENIX FAST 2013, pages 243 to 256 (USENIX PDF); Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives, Cai, Ghose, Haratsch, Luo, and Mutlu, Proceedings of the IEEE, September 2017 (arXiv 1706.08642, section 6); Flash Reliability in Production: The Expected and the Unexpected, Schroeder, Lagisetty, and Merchant, USENIX FAST 2016 (USENIX PDF, sections 3 and 4).

Limits

Table

13 rows, the same rows as the CSV. Value low and value high are the printed range ends, or a single printed value in the high column. Units are in the unit column. Sources are the pages opened on 2026-10-11.
MeasureValue lowValue highUnitScopeNoteCitation
Target uncorrectable bit error ratenot stated0.0000000000000001errors per bit readContemporary SSD makers, as cited by Cai et al.Zhao et al. use 1e-15 as the decoding failure target.cai-procieee17-pdf
Highest raw bit error rate an example BCH code corrects at that targetnot stated0.001raw bit errors per bitCode rate 0.935, one hard readExample code chosen by the survey, not every drive's code.cai-procieee17-pdf
Highest raw bit error rate an example soft LDPC code corrects at that targetnot stated0.005raw bit errors per bitCode rate 0.936, soft decoding with extra readsHard-decision LDPC alone is similar to BCH.cai-procieee17-pdf
Extra reads of the example combined hard and soft LDPC schemenot stated0.28percent more reads than BCHIf 0.01% of codewords fail and soft LDPC needs seven extra readsWorst case, four codewords per flash page; the survey says this gives twice BCH's correction strength.cai-procieee17-pdf
Raw bit error rate tolerance of soft LDPC relative to BCHnot stated3times25nm MLC chip model, six extra sensing levels, 1e-15 targetHard-decision LDPC tolerates only slightly more than BCH.zhao-fast13-pdf
Redundancy of the LDPC code in the simulationnot stated512bytes per 4 KB of user dataRate 8/9 codeThe same overhead is used for the BCH comparison.zhao-fast13-pdf
Worst-case read response time increase with soft decoding at 10,000 program/erase cyclesnot stated100percent (lower bound)Read-intensive traces, simulated SSDPrinted as over 100%.zhao-fast13-pdf
Worst-case read response time increase with the authors' three techniquesnot stated20percent (upper bound)Same tracesPrinted as below 20%.zhao-fast13-pdf
Hard-decision LDPC decoding failure probability across the life of the flash0.0000000000000010.01probability per readEarly life to late lifeSoft decoding is only needed once failures become common.zhao-fast13-pdf
Median raw bit error rate of first-generation drive models0.000000000580.00000003raw bit errors per bit readGoogle data centers, several drive modelsPrinted as 5.8e-10 to more than 3e-8; MLC far higher than SLC.schroeder-fast16-pdf
99th percentile raw bit error rate across models0.0000000220.000027raw bit errors per bit readSame drives; SLC-B lowest, MLC-D highestThe 99th percentile drive is usually at least 10 times the median of its model.schroeder-fast16-pdf
Drive days with an uncorrectable error26per 1,000 drive daysSame drivesCorrectable errors affect the majority of drive days.schroeder-fast16-pdf
Drives with non-final read errors that retries can recovernot stated2percent of drives (upper bound)Same drivesPrinted as less than 2%; final read errors are about two orders of magnitude more common.schroeder-fast16-pdf

Columns

measure (string)
The quantity as the source names it.
value_low (number)
Lower end of a printed range. Empty when the source prints a single value.
value_high (number)
Single printed value, or the upper end of a range. For 'over' or 'below' it is the stated bound.
unit (string)
Unit of the value columns: errors per bit, percent, times, bytes, probability, or per 1,000 drive days.
scope (string)
Population and window the value applies to.
note (string)
What the value is not, or the source wording behind it.
citation_id (string)
Id of the opened source in the citations list.

License

Small derived table of figures printed in Zhao et al. (FAST 2013), Cai et al. (Proceedings of the IEEE 2017), and Schroeder et al. (FAST 2016), with credit. Not a Creative Commons license. The papers remain with their authors or publishers. This file is not a copy of the papers and not the data.

Sources

  1. LDPC-in-SSD: Making Advanced Error Correction Codes Work Effectively in Solid State Drives, Zhao, Zhao, Sun, Zhang, Zhang, and Zheng, USENIX FAST 2013, pages 243 to 256 (USENIX PDF) (accessed 2026-10-11)
  2. Error Characterization, Mitigation, and Recovery in Flash-Memory-Based Solid-State Drives, Cai, Ghose, Haratsch, Luo, and Mutlu, Proceedings of the IEEE, September 2017 (arXiv 1706.08642, section 6) (accessed 2026-10-11)
  3. Flash Reliability in Production: The Expected and the Unexpected, Schroeder, Lagisetty, and Merchant, USENIX FAST 2016 (USENIX PDF, sections 3 and 4) (accessed 2026-10-11)