hesela.devLeaFTL
LeaFTL is a research flash translation layer that compresses logical-to-physical page mappings into learned linear segments.
Approximate segments have a bounded address error. The predicted page's out-of-band metadata identifies neighboring logical pages, allowing correction with one additional flash access in the described design. This is address verification, not permission to return an approximate payload. [1]
The published evaluation includes both a simulator and an open-channel SSD prototype. The latter runs the FTL on the host; it is not a survey of retail SSD firmware. [1]
The public artifact documents simulation experiments using WiscSim, PyPy2 and external traces, with substantial CPU and memory requirements. [2]
Without protected DRAM, the described recovery scans flash, rebuilds block-validity counters and relearns recently allocated blocks. The prototype's reported 101.3 ms mean segment-reconstruction time is only one component of its 15.8-minute mean recovery, measured after intentional system restarts. These are author-reported prototype results, not a retail-SSD recovery bound. [1]
Relations
- related
- Flash translation layer (FTL), SSD mapping cache, FTL translation page, Page-level mapping (FTL), Reverse mapping (FTL)
Advantages
- Compressing mappings can leave more controller memory available for data caching. [1]
Limitations
- Lookup correction relies on the bounded-error and metadata design; compression alone does not establish crash consistency or a universal latency bound. [1]
Citations
- Sun et al. LeaFTL: A Learning-Based Flash Translation Layer for Solid-State Drives. ASPLOS 2023, sections 3-5; DOI 10.1145/3575693.3575744.
- LeaFTL author artifact: simulation setup, workloads and reproduction commands.
Further reading
Sources & caveats
- Primary-source synthesis. No benchmark replication, power-cut experiment or independent peer review is claimed. LeaFTL (ASPLOS 2023) and LearnedFTL (HPCA 2024) are distinct designs.