hesela.devWise Ordering for Writes
Wise Ordering for Writes is a write-cache destaging policy that combines logical-address ordering with a reference bit to retain recently hit write groups.
WOW destages dirty groups in circular address order. A new group starts with its recency bit clear; a group-level write hit sets it. The pointer clears and skips set bits. In the paper's CLOCK variant, new groups enter immediately behind the destage pointer; hits set a bit without moving the hit group. WOW inserts by address instead. CLOCK does not maintain LRU's exact recency order. [1] [9]
A write-group hit is not necessarily an overwrite of a cached page. RAID-5 uses stripe groups; RAID-10 uses strip groups. A group hit can be a page miss, so gathering different pages and replacing an earlier page value have different effects. The lookup tests group membership. Groups may be partially populated; a group hit alone does not establish full-stripe coverage. [7] [8]
Section III.F.1 describes suppressing sequential-access bit updates. Figure 4, lines 2-6, retains a separate page-hit assignment outside the sequential test. A sequential group hit with a page miss leaves the bit unchanged, not necessarily clear. This prose/pseudocode discrepancy does not establish the evaluated implementation. [2] [10]
Victim order and drain concurrency are separate decisions. The evaluation varies outstanding destages with cache occupancy, balancing incoming writes against read interference instead of permanently using maximum queue depth. [4]
The experiment called its shared-memory write cache NVS, but used volatile DDR without battery backup. It omitted a separate read cache while still serving hits from the write cache. The SPC-1 Like workload used an earlier prototype implementation. These are performance-method details, not a power-failure test or a certified SPC-1 result. [5] [6]
Relations
Limitations
- The destage pointer is not a physical disk-head position: concurrent reads, RAID read-modify-write and lower-layer reordering can move the heads independently. [3]
- The reference bit and address order do not establish durability; the cited cache experiment did not provide battery-backed persistence. [5]
Citations
- Gill and Modha. WOW: Wise Ordering for Writes. FAST 2005. Section III.B, algorithm and insertion/reference-bit rules.
- Gill and Modha. WOW: Wise Ordering for Writes. FAST 2005. Section III.F.1, sequential-write enhancement.
- Gill and Modha. WOW: Wise Ordering for Writes. FAST 2005. Section III.D, limits of the disk-head analogy.
- Gill and Modha. WOW: Wise Ordering for Writes. FAST 2005. Section IV.E, occupancy-dependent destage concurrency.
- Gill and Modha. WOW: Wise Ordering for Writes. FAST 2005. Section IV.C, volatile experimental NVS and read-cache scope.
- Gill and Modha. WOW: Wise Ordering for Writes. FAST 2005. Section V.B, earlier prototype SPC-1 Like workload.
- Gill and Modha. WOW: Wise Ordering for Writes. FAST 2005. Section III.A: strip/stripe groups and page-hit versus group-hit scope.
- Gill and Modha. WOW: Wise Ordering for Writes. FAST 2005. Section III.F.3: hit lookup tests write-group membership.
- Gill and Modha. WOW: Wise Ordering for Writes. FAST 2005. Section III.C, CLOCK comparison and new-group insertion position.
- Gill and Modha. WOW: Wise Ordering for Writes. FAST 2005. Figure 4, lines 1-14, printed p.134; compare section III.F.1, p.135.
Sources & caveats
- Primary-paper source review, not a reimplementation, reproduced benchmark or hardware fault-injection experiment. No numerical speedup is inferred for present-day SSDs or for Hesela's transfer-count model.
- The paper's NVS name describes the intended controller role; its experimental memory was volatile. The evaluation and sequential-write enhancement are distinguished from the basic victim-selection rule.