buffer-cycle-deadlock · unknown · also Cyclic buffer dependency

Buffer-cycle deadlock

Buffer-cycle deadlock occurs when frames hold buffers while each waits for another buffer in a closed dependency chain.

Related Observatory article: Buffer-cycle deadlock on hesela.com

The 1996 Fibre Channel study models dependencies induced by permitted routes between switch input buffers. A cycle-free dependency graph provides deadlock-free routing within that model. This is a statement about resource dependencies, not simply the presence of a loop in the cabling. [1]

A zero-credit counter alone does not identify such a cycle. Investigate the forwarding paths and occupied resources before attributing a stall to deadlock.

Relations

related
Fibre Channel, Buffer-to-buffer credit, Fibre Channel frame

Citations

  1. Cherkasova, Kotov and Rokicki. Fibre Channel Fabrics: Evaluation and Design. HICSS 1996, sections 2.1 and 3. DOI 10.1109/HICSS.1996.495447. (accessed 2026-10-19)
Sources & caveats
  • Historical architectural model; no claim about current vendor routing implementations or measured deadlock incidence.

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Hesela team. Buffer-cycle deadlock. Hesela. 2026-10-19. https://hesela.dev/terms/buffer-cycle-deadlock/