FIS-based switching (SATA)
FIS-based switching allows a SATA host to keep commands outstanding to multiple devices behind a port multiplier.
The controller preserves each target's context while interleaving FIS traffic. Concurrent device activity still shares one upstream link. [1] [2]
In AHCI, CAP.FBSS and PxCMD.FBSCP report global and per-port capability; PxFBS.EN enables operation. CAP.SPM alone is insufficient. The host port's CAP.NCS + 1 slots remain a shared budget, not a fresh queue per downstream disk. [3]
Error recovery can pause other targets. When PxFBS.SDE is set, PxFBS.DWE identifies the affected target; other commands pause until software acknowledges and clears the condition through PxFBS.DEC. Other devices resume after hardware clears PxFBS.DEC; the affected device may still need a software reset. A DEC timeout or additional timeouts call for broader recovery. This differs from non-device-specific recovery, which flushes all commands on the port. [4]
With several targets active, PxTFD may reflect different devices and is unsafe for command-completion decisions. AHCI directs software to PxCI and PxSACT instead; its exception is commands outstanding to only one device. [5]
Relations
- related
- SATA port multiplier, SATA Frame Information Structure, Command-based switching (SATA), AHCI, Native Command Queuing
Citations
- SATA-IO Serial ATA Revision 2.6, section 16.7, page 545: command-based and FIS-based switching
- Scott Knowlton, Synopsys: Understanding SATA FIS-Based Switching (2013), connectivity and shared bandwidth
- Intel AHCI 1.3.1, sections 3.1.1, 3.3.7, 3.3.16 and 9: capabilities and port-multiplier operation
- Intel AHCI 1.3.1, sections 9.3.6.1-9.3.6.2 and 9.3.8: device-specific recovery and host-port reset
- Intel AHCI 1.3.1, section 9.3.7: PxTFD register information
Sources & caveats
- SATA-IO sections were checked through indexed primary-specification text; direct PDF retrieval was unavailable. [1]