hesela.devMajor-minor loop architecture
Major-minor loop architecture organizes bubble memory into smaller storage loops connected by transfer elements to shared read and write access paths.
The minor loops retain and circulate stored domains. Transfer operations connect selected data positions to the access paths instead of requiring one serial path through every stored bit. The topology reduces the long-loop access problem, but positioning and transfer still take time. [1]
Loop redundancy addresses defective paths. A documented implementation stores a loop map and index in a bootstrap loop, allowing support circuitry to exclude bad-loop positions. This selection is distinct from correcting errors in data read from usable loops. [2]
Relations
- related
- Bubble memory, Disk defect skipping
Citations
- R. B. J. Warnar and P. J. Calomeris: NBS SP 500-1, January 1977, pp. 1-4, 13, 30-34; historical technology survey
- Intel Magnetics: Bubble Memory Design Handbook, May 1979, printed pp. 1-3, 23; 7110/7112 and 7242
Sources & caveats
- The Intel May 1979 handbook describes the 7110/7112 family and 7242 formatter; its loop-map details are implementation-specific. [2]