nand-plane · shipping · also flash plane

NAND plane

A NAND plane is an array subdivision within a logical unit that groups erase blocks.

Related Observatory article: NAND plane on hesela.com

Supported multi-plane operations combine the same operation type across distinct plane addresses in one LUN. They do not grant arbitrary independent execution to every plane. Address restrictions depend on the operation and reported capabilities; follow the exact specification and device parameter page. [1]

Geometry accounting matters: Linux's eraseblocks_per_lun already counts the blocks across that LUN. Its capacity calculation multiplies targets, LUNs per target, blocks per LUN, pages per block and data bytes per page, without another planes multiplier. [2]

Relations

related
NAND logical unit, NAND target, NAND erase block, NAND page, NAND copyback

Citations

  1. ONFI 5.2, section 7: multi-plane operations and device-specific address restrictions (accessed 2026-10-20)
  2. Linux v6.12, include/linux/mtd/nand.h: nand_memory_organization, nand_pos and nanddev_target_size (accessed 2026-10-20)
Sources & caveats
  • ONFI terminology is scoped to the cited editions; component geometry and supported command sequences must be checked for the selected device.

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Hesela team. NAND plane. Hesela. 2026-10-20. https://hesela.dev/terms/nand-plane/