hesela.devNVMe Phase Tag
The NVMe Phase Tag is a one-bit marker used in memory-based completion queues, including PCIe, to distinguish new entries from old contents of a reused slot.
Scope: The expected phase alternates on each traversal of the completion ring. The bit is reserved in NVMe over Fabrics; it is not a transport-independent completion mechanism. [1]
Processing: Linux v6.12 checks the expected bit, uses a DMA read barrier before processing the entry, and flips its expected phase when the head wraps. [2]
Meaning: Freshness is separate from command status. A matching phase can accompany an error; it is not proof of a durable write. [1]
Relations
Citations
- NVM Express Base 2.0d, sections 3.3.1.2, 3.3.2.1.1-2 and 3.3.3; copyright 2008-2024 NVM Express, Inc., all rights reserved
- Linux v6.12: NVMe PCIe completion phase, DMA barrier and ring wrap
Sources & caveats
- Versioned sources explain protocol and implementation behavior; no hardware experiment or performance claim.