hesela.devNVMe Physical Region Page
An NVMe Physical Region Page entry identifies a memory page or page portion used to transfer a command's data buffer.
For ordinary PRP-based Read and Write commands, PRP1 can start within the first memory page. When PRP1 alone is insufficient, PRP2 identifies a second data page or a list of additional page addresses [1]. The page is transfer memory, not NAND geometry.
With a 4 KiB controller memory page, an 8 KiB transfer starting at offset zero spans two pages; at offset 512 it spans three and needs a PRP list. This is address-span arithmetic, not a speed measurement [3].
On PCIe, buffer pointers contain device-visible DMA addresses, which an IOMMU can translate; an application pointer is not directly interchangeable with them [4].
List storage is separate: the initial list pointer may be 8-byte aligned within a page; later list pages are page-aligned. A page-aligned 4 KiB list has 512 slots, but a non-final list spends one on a link, leaving 511 data addresses. A nonzero starting offset reduces its slots [2].
Relations
- related
- nvme, nvme-sgl
Citations
- NVM Express 1.0e: revision history and PRP-based Read/Write; copyright 2007-2014 NVM Express, Inc., all rights reserved
- NVM Express Base 2.0a, sections 2 and 4.1; copyright 2007-2021 NVM Express, Inc., all rights reserved
- Linux v6.12: NVMe PCIe data mapping and PRP/SGL construction
- Linux 6.12: Dynamic DMA mapping guide, CPU and DMA addresses