pcie-active-state-power-management · shipping · also ASPM, PCIe ASPM

PCIe Active State Power Management

PCIe Active State Power Management reduces link power during inactivity through supported low-power link states.

Related Observatory article: PCIe Active State Power Management on hesela.com

Link scope: ASPM includes L0s and L1 link states, with additional L1 substates where supported. It is separate from the NVMe controller's power-state table. Linux v6.12 checks link capabilities and acceptable exit latencies when deciding which states may be enabled. [1]

Platform policy: Link power settings can differ between AC and battery operation. An enabled NVMe APST policy therefore does not establish the PCIe link policy, and disabling APST does not by itself disable ASPM. [2]

Diagnostic inference: A first request after inactivity can encounter both link and controller wake paths. Configuration identifies permitted behavior, not proof that a specific transition caused a measured delay. [2]

Relations

related
NVMe Autonomous Power State Transition, SSD thermal throttling

Citations

  1. Linux v6.12: PCIe ASPM capability and latency checks (accessed 2026-10-21)
  2. Microsoft Learn: StorNVMe power management, idle states and PCIe ASPM (accessed 2026-10-21)
Sources & caveats
  • Linux v6.12 implementation and Microsoft platform documentation are used for scope distinctions, not a universal latency estimate.

JSON: /data/terms/pcie-active-state-power-management.json

Published by Hesela team · Updated

Report a correction · Editorial standards · Reuse guidance

Cite this page
Hesela team. PCIe Active State Power Management. Hesela. 2026-10-21. https://hesela.dev/terms/pcie-active-state-power-management/