hesela.devTPFTL
TPFTL is a research flash translation layer that groups cached address mappings by translation page and manages them with two levels of LRU lists.
A page-level list orders translation-page groups; each group holds an entry-level list of selected mappings. Grouping entries does not require caching a whole translation page. [1]
Replacement first chooses the least-recently-used group, then its oldest clean entry if available. Evicting a dirty entry writes back that group's dirty mappings together; nonvictim entries remain cached and become clean. [1]
Prefetching uses request length and detected sequentiality. Its span is constrained by the requested translation-page boundary and the number of entries in the replacement group, limiting the extra metadata work. [1]
A GC-only account of DFTL batching is too narrow. DFTL section 3.2 also discusses cached mappings sharing a victim's translation page. TPFTL section 4.4 emphasizes the GC case when describing DFTL. This textual difference does not establish how the later comparison's DFTL baseline was implemented or invalidate its reported results. [2] [1]
Four synthetic replacement witnesses separate the chosen victim from the writeback set. In one constructed state, three dirty mappings are written back but only one is evicted; the other two remain clean in cache. These are deterministic state transitions, not FlashSim replication or SSD performance measurements. [3]
Relations
- related
- Flash translation layer (FTL), SSD mapping cache, FTL translation page, Page-level mapping (FTL), Global Translation Directory (DFTL), Least recently used replacement, Write amplification
Limitations
- The original evaluation uses FlashSim with four enterprise traces; its metadata-write reductions are not whole-device endurance measurements. [1]
Citations
- Zhou et al. An Efficient Page-level FTL to Optimize Address Translation in Flash Memory. EuroSys 2015, sections 4-5.
- Gupta, Kim and Urgaonkar. DFTL. ASPLOS 2009, sections 3.2-3.3 (PDF pages 6-7).
- Hesela: TPFTL replacement-state witnesses, synthetic inputs and exact transitions.
Sources & caveats
- Original EuroSys 2015 full text reviewed; later FEMU reimplementations have different experimental settings. No implementation reproduction or commercial adoption is established.
- DFTL section 3.2 and TPFTL section 4.4 reconciled on 2026-11-09. The synthetic Python model and tests are in /research/tpftl-replacement/; it does not implement DFTL, prefetching, GC, timing or crash recovery.