ultra-dma · unknown · also UDMA, Ultra ATA

Ultra DMA

Ultra DMA is a family of ATA data-transfer modes with mode-specific timing and CRC protection for interface transfers.

Related Observatory article: Ultra DMA on hesela.com

Mechanism: In the ATA/ATAPI-5 draft, Ultra DMA transfers use both edges of a data strobe. Timing follows the selected mode, and each burst ends with CRC checking. [4]

Scope: A transfer mode describes the interface path, not the disk's mechanical data rate. For example, one PATA notebook manual separately specifies 100 MB/s for Ultra DMA mode 5 and 45.8 MB/s for sustained outer-diameter transfers. These are product specifications, not a benchmark. [2]

Compatibility: Faster modes require compatible host and device support plus the specified connection. For a documented desktop implementation, modes 3 and 4 require an 80-conductor, 40-pin cable. Extra ground conductors improve signal integrity without adding data bits. [3] [1]

Integrity: Ultra ATA/66 uses CRC for transferred data. That interface check does not establish an end-to-end file-integrity or persistence guarantee. [1]

Completion: The draft distinguishes burst termination from command completion. An unfinished command can continue in a later burst; CRC success is not its final status. This protocol distinction is separate from the end-to-end and persistence limitations above. [4]

Relations

related
PATA, IDE / ATA, Serial ATA (SATA)

Limitations

  • A supported maximum mode does not establish the active mode or sustained application throughput. [1, 2]

Citations

  1. Western Digital: Ultra ATA/66 FAQ, April 1999, questions 2-7 (accessed 2026-10-25)
  2. Seagate: Momentus 7200.1 PATA Product Manual, Rev. C, August 2007, sections 2.5 and 4.1 (accessed 2026-10-25)
  3. Seagate: Barracuda ATA II Product Manual, Rev. A, February 2000, introduction and section 2.2.4 (accessed 2026-10-25)
  4. T13/1321D revision 3: ATA/ATAPI-5 working draft, 29 February 2000, sections 6.6.1 and 6.6.2.3 (accessed 2026-10-25)
Sources & caveats
  • The 100 MB/s and 45.8 MB/s example is from Seagate's Momentus 7200.1 PATA manual, Rev. C, section 2.5.
  • The end-to-end integrity limitation is an engineering inference from the narrower interface-transfer scope of the CRC.
  • The linked d1153r17.pdf file identifies itself as T13/1321D revision 3, ATA/ATAPI-5, on its cover; it is a working draft, not an approved standard.
  • Historical interface documentation does not establish a single current end-of-life status for all implementations.

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Hesela team. Ultra DMA. Hesela. 2026-10-25. https://hesela.dev/terms/ultra-dma/