hesela.devAsynchronous DRAM Refresh
Asynchronous DRAM Refresh is a platform power-fail mechanism that drains covered memory-controller write-pending buffers to persistent memory without protecting dirty CPU caches.
In Intel's documented persistent-memory platform, data that reaches the covered controller queue can survive power loss, while cache-resident updates require software persistence operations. [1] The name does not mean ordinary DRAM automatically becomes nonvolatile; protection depends on the platform and backing medium. eADR extends the protected boundary to CPU caches. [2]
Relations
- related
- persistence-domain, eadr, persistent-memory, persistence-ordering