hesela.devExtended Asynchronous DRAM Refresh
Extended Asynchronous DRAM Refresh is a platform capability that extends persistent-memory power-fail protection to CPU caches.
Intel's third-generation Xeon overview states that supported, detected eADR removes explicit cache-flush requirements but still requires SFENCE and adequate platform stored energy. This is a system capability, not a guarantee inferred solely from a CPU model. [1] PMDK's byte persistence granularity still permits ordering barriers; a larger persistence domain is not an application transaction. [2]
Relations
- related
- adr, persistence-domain, persistent-memory, persistence-ordering