hesela.devNVMe doorbell
An NVMe PCIe doorbell communicates a submission-queue tail or completion-queue head position from host software to the controller.
An SQ-tail update announces submitted commands. A CQ-head update returns consumed completion slots for reuse. Either update can cover a batch; it is not a transfer of the command or read/write payload itself [1]. Reading a CQ entry alone does not release its slot; the controller needs the updated head [3].
Linux v6.12 writes the tail or head value through distinct PCIe register locations. With doorbell-buffer support configured, its event-index check can avoid a register write. Counting MMIO doorbell writes therefore does not directly count I/O commands [2].
Relations
Citations
- SPDK: Submitting I/O to an NVMe Device
- Linux v6.12: NVMe PCIe queue submission, completion handling and doorbell-buffer checks
- NVM Express Base 2.0a, section 3.3.1.2; copyright 2007-2021 NVM Express, Inc., all rights reserved
Sources & caveats
- The memory-ring description is PCIe-scoped; NVMe over Fabrics uses transport-specific messaging.
- Historical specification and pinned implementation references describe mechanisms, not current feature coverage or measured performance.