hesela.devNVMe submission queue
On the NVMe PCIe path, a submission queue is a memory ring where host software places commands for a controller to consume.
The command ring is separate from read/write payload buffers. Host software fills free command slots and publishes a new tail position through a doorbell, which can announce several commands together [1].
Each I/O submission queue has an associated completion queue; several I/O submission queues may share one. The Admin queues remain one-to-one. An advancing SQHD reports consumed command slots, not completed commands [2].
SQHD is captured when the completion entry is created; the controller may have consumed more slots before the host reads that entry [2].
Relations
- related
- NVMe, NVMe completion queue, NVMe doorbell, NVMe Physical Region Page, NVMe Scatter Gather List, Queue depth, NVMe Command Identifier
Citations
- SPDK: Submitting I/O to an NVMe Device
- NVM Express Base 2.0a, sections 2.1-2.2, 3.1.1, 3.3.1.2 and 3.3.3.2; copyright 2007-2021 NVM Express, Inc., all rights reserved
Sources & caveats
- The memory-ring description is PCIe-scoped; NVMe over Fabrics uses transport-specific messaging.
- Historical specification and pinned implementation references describe mechanisms, not current feature coverage or measured performance.