pcie-flit · unknown · also PCIe flow control unit, PCIe Flit Mode

PCIe FLIT

A PCIe FLIT is a fixed-size flow-control unit used in PCI Express Flit Mode to carry transaction packets together with link-control and error-protection information.

PCI-SIG documents the same 256-byte layout for PCIe 6.0 and 7.0: 236 bytes for Transaction Layer Packets (TLPs), 6 for Data Link Layer Payload (DLP), 8 for CRC and 6 for forward error correction (FEC) [1]. The TLP region includes packet headers, so 236/256 is not application-data efficiency.

Packet boundaries need not coincide with FLIT boundaries. A FLIT can carry multiple TLPs or only part of one, and a TLP can span FLITs [2]. This fixed framing supports link error protection; it does not define an NVMe command, logical block, persistence guarantee or SSD transfer rate.

The link can retain FLIT mode after reducing its speed [2]. Therefore a rate alone does not justify applying the earlier 128b/130b non-FLIT formula. See the storage-interface-payload-ceilings dataset for explicit accounting fields.

Relations

related

PCIe storage attachment, PCIe 5.0 storage, NVMe

Advantages

• Fixed-size framing supports the link's CRC and FEC mechanisms. [1]
• TLPs can be packed across FLIT boundaries rather than requiring one FLIT per transaction. [2]

Limitations

• The TLP byte region still includes headers and can be incompletely occupied; its capacity is not measured application throughput. [2]
• FLIT-mode accounting differs from earlier non-FLIT line encoding even when a link operates at a lower speed. [2]

Citations

1. PCI-SIG: PCIe 7.0 specification webinar Q&A (3 September 2025), question 1 (accessed 2026-10-20)
2. PCI-SIG: PCIe 6.0 webinar Q&A on FLIT mode (19 August 2021), introduction and questions 3, 6-9 (accessed 2026-10-20)

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