controller-memory-buffer · shipping · also CMB

Controller Memory Buffer (CMB)

Controller Memory Buffer is an optional NVMe mechanism that exposes controller-resident memory for host use through PCIe.

The controller advertises supported uses, which may include queues, descriptors or transfer data. HMB instead assigns host memory to the controller. CMB is not a synonym for an SSD's private DRAM cache. [1]

Relations

related

hmb, nvme, pcie-storage, dram-cache-ssd

Advantages

• Supported queue and descriptor placement can avoid fetching these structures from host memory. [1]

Limitations

• Available uses depend on controller capability flags; CMB does not itself establish persistent-memory or power-loss-protection guarantees. [1]

Citations

1. NVM Express 1.4a (9 March 2020), sections 4.7 and 4.8: CMB and PMR. Copyright 2007-2020 NVM Express, Inc. (accessed 2026-10-18)

Further reading

2. Hesela: Host Memory Buffer (HMB). (accessed 2026-10-18)

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