dftl · research · also Demand-based Flash Translation Layer

DFTL

DFTL is a research flash translation layer that caches selected page-level address mappings in RAM while keeping mapping pages on flash.

The Cached Mapping Table holds selected data-page mappings; the Global Translation Directory locates their translation pages. Mapping granularity and RAM residency are separate choices. [1]

An unchanged victim can be discarded without metadata writeback. A modified victim requires a translation-page update and directory adjustment. [1]

Demand caching favors temporal reuse; the original implementation uses segmented LRU. DFTL names a specific design, not every partially cached FTL. [1]

Relations

related
Global Translation Directory (DFTL), SSD mapping cache, Page-level mapping (FTL), FTL translation page, Flash translation layer (FTL), TPFTL

Limitations

  • The original evaluation uses FlashSim and workload traces; its results do not establish the performance of current commercial SSDs. [1]

Citations

  1. Gupta, Kim and Urgaonkar. DFTL: A Flash Translation Layer Employing Demand-based Selective Caching of Page-level Address Mappings. ASPLOS 2009. (accessed 2026-11-09)

Further reading

  1. Hesela: SSD mapping caches and host memory (accessed 2026-11-09)
Sources & caveats
  • Source synthesis from the original paper, sections 3-5; no experiment reproduced here.

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Cite this page
Hesela team. DFTL. Hesela. 2026-11-09. https://hesela.dev/terms/dftl/